This invention relates generally to stacked capacitor memory cells, and more particularly to a method of reducing the storage node leakage current in the memory cell.
A partially formed stacked capacitor memory cell is shown in FIG. 1. In pertinent part, the partially formed memory cell includes a P-type substrate 10, polysilicon wordlines 12A and 12B, a first TEOS oxide layer 14A, a thick field oxide layer 16, and a channel stop layer 18. The polysilicon wordline 12A is insulated from the P-type substrate by a thin oxide layer 13. The first TEOS oxide layer 14A is about 1000 Angstroms thick. Referring now to FIG. 2, the partially formed memory cell is blanket implanted with a light N-type dopant implant of phosphorous to form the source and drain of the memory cell access transistor. The phosphorous dopant is implanted with a density of between 1.5 and 2.0.times.10.sup.13 /cm.sup.2. N-type diffusions 20 and 28 can function as both drain and source of the memory cell access transistor, depending upon whether the memory cell is being read from or written to. Diffusion 20 is subsequently referred to as the "storage node" and diffusion 28 is subsequently referred to as the "bitline contact". Referring now to FIG. 3, a second TEOS oxide layer 14B is deposited on top of the first TEOS oxide layer 14A. The second TEOS oxide layer has a thickness of about 2000 Angstroms.
Referring now to FIG. 4, the first and second TEOS layers 14A and 14B, along with a patterned photoresist layer 15 are etched between wordline 12A and the field oxide layer 16 to form a buried contact window 17. The photoresist layer 15 is stripped and the first and second oxide layers are shown as a single oxide layer 14 in FIG. 5. Referring now to FIG. 6, the first polysilicon plate 22 of a stacked capacitor is formed and electrically contacts N-type storage node 20. The first plate 22 of the stacked capacitor is heavily doped with an N-type dopant to form an ohmic contact to storage node 20. The polysilicon storage node capacitor plate 22 is ideally highly doped to a level that allows for good conduction. A typical sheet resistivity for good conduction is in the range of 125 to 300 ohms per square, or less. During subsequent processing steps, however, the depth and lateral extent of storage node 20 increases, primarily because of outdiffusion from the heavily doped capacitor plate 22. Drain 20 expands from about 0.3 microns to drain 20', which is about 0.5 microns or more. FIG. 7 shows the second capacitor plate 26 and dielectric oxide/nitride/oxide ("ONO") layer 24.
Outdiffusion of storage node 20 has a negative impact upon the performance of the memory cell. Normal process and masking variations, as well as the dimensions of the outdiffused drain 20', cause dopants to migrate close to the bitline contact 28 and create a leaky memory cell access transistor. Ideally, when the access transistor is off, it forms a high impedance series resistance and the memory cell has no leakage current. A leaky access transistor, however, bleeds charge off of the storage node 20, effectively diminishing the effective size of the memory cell storage capacitor.
What is desired is a method for minimizing the leakage current from the storage node of a stacked capacitor memory cell due to outdiffusion from a highly doped stacked capacitor plate into the storage node.